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M45PE40-VMP6 データシート(PDF) 12 Page - STMicroelectronics

部品番号 M45PE40-VMP6
部品情報  4 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 33 MHz SPI Bus Interface
PDF  35 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M45PE40-VMP6 データシート(HTML) 12 Page - STMicroelectronics

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Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Write (PW), Page Program (PP),
Page Erase (PE), and Sector Erase (SE) instruc-
tion.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 7. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
–Power-up
–
Write Disable (WRDI) instruction completion
–
Page Write (PW) instruction completion
–
Page Program (PP) instruction completion
–
Page Erase (PE) instruction completion
–
Sector Erase (SE) instruction completion
Figure 8. Write Disable (WRDI) Instruction Sequence
C
D
AI02281E
S
Q
2
1
34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
2
1
34567
High Impedance
0
Instruction



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