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UPD360 データシート(PDF) 40 Page - Microchip Technology |
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UPD360 データシート(HTML) 40 Page - Microchip Technology |
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40 / 221 page ![]() UPD360 DS00002084C-page 40 2016-2017 Microchip Technology Inc. 3. Software programs the General Purpose Timer Load Register (GP_TIMER_LOAD) to a random value that com- plies with the range for tDRP period as defined in the USB Type-C Specification. 4. Software sets the ENABLE, RESET and DIS_ON_UFLOW bits in the General Purpose Timer Control Register (GP_TIMER_CTL). This causes the value in the General Purpose Timer Load Register (GP_TIMER_LOAD) to be loaded into the timer and it begins decrementing. This also configures the timer to delay assertion of GP_U- FLOW in the General Purpose Timer Interrupt Source Register (GP_TIMER_INT_SRC) until the timer is fully dis- abled . APPLICATION NOTE: Writes to General Purpose Timer Load Register (GP_TIMER_LOAD) and General Purpose Timer Control Register (GP_TIMER_CTL) defined in the prior steps may be done in the same I2C write burst. 5. Upon timer expiration, the GP_UFLOW bit will be set and the GP_TIMER_INT asserts in Interrupt Status Register (INT_STS). 6. The IRQ_N pin asserts. 7. Software services the IRQ and determines whether or not a connection has been established with a UFP, or DFP. If no connection has been established, software changes the device’s role. See Section 9.4, "DRP Operation" for further details. 8. Software programs the General Purpose Timer Load Register (GP_TIMER_LOAD) to a random value that com- plies with the range of the tDRP period as defined in the USB Type-C Specification. 9. Software shall clear the GP_UFLOW bit in the General Purpose Timer Interrupt Source Register (GP_TIM- ER_INT_SRC). 10. Software sets the ENABLE, RESET and DIS_ON_UFLOW bits in General Purpose Timer Control Register (GP_- TIMER_CTL). This causes the value in General Purpose Timer Load Register (GP_TIMER_LOAD) to be loaded into the timer and the timer begins decrementing. APPLICATION NOTE: Writes to the General Purpose Timer Load Register (GP_TIMER_LOAD), General Purpose Timer Interrupt Source Register (GP_TIMER_INT_SRC) and General Purpose Timer Control Register (GP_TIMER_CTL) defined in the prior steps may be done in the same I2C write burst. 11. Upon timer expiration, and timer disablement, the GP_UFLOW bit will be set and the GP_TIMER_INT asserts in Interrupt Status Register (INT_STS). 12. The IRQ_N pin asserts. 13. Software services the IRQ and determines if a connection has been established with a UFP, or DFP. If no con- nection has been established SW changes the device’s role. See Section 9.4, "DRP Operation" for further details. 14. Goto step 8. |
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