LD3986 datasheet(3/12 Pages) STMICROELECTRONICS

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LD3986 データシート(PDF) 3 Page - STMicroelectronics

部品番号	LD3986

部品情報	DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS

PDF	12 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

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3 / 12 page

LD3986 SERIES

3/12

Figure 2: Pin Connection (top through view)

Table 4: Pin Description

Figure 3: Typical Application Circuit

Symbol

Pin N°

Name and Function

VO2

Output Voltage 2 of the dual LDO

EN2

Enables voltage for output voltage 2: ON MODE when VEN ≥ 1.4V, OFF MODE when VEN ≤

0.4V (Do not leave floating, not internally pulled down/up)

BYPASS

Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise voltage

GND

Common Ground

GND

Common Ground

EN1

Enables voltage for output voltage 1: ON MODE when VEN ≥ 1.4V, OFF MODE when VEN ≤

0.4V (Do not leave floating, not internally pulled down/up)

VO1

Output Voltage 1 of the dual LDO

Input Voltage for both LDO

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