CS4210 datasheet(71/102 Pages) NSC

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cycleSynch

RSCU

Undef

Cycle Synchronous: Indicates that a new isochronous cycle has started.

Set when the low order bit of the internal IsochCycleTimer.cycleCount

(BAR0+Offset F0h[24:12]) toggles.

phy

RSCU

Undef

Physical Layer: Generated when the CS4103 requests an interrupt

through a status transfer.

RSVD

Reserved

busReset

RSCU

Undef

Bus Reset: Indicates that the CS4103 has entered bus reset mode. See

Section 4.4.16.2 "Bus Reset" on page 72 for information on when to clear

this interrupt.

selfIDcomplete

RSCU

Undef

Self-ID Complete: A Self-ID packet stream has been received. Is set at the

end of the bus initialization process if LinkControl.rcvSelfID (BAR0+Offset

E0h[9]) is set. This bit is turned off simultaneously when IntEvent.busReset

(bit 17) is turned on.

15:10

RSVD

Reserved

lockRespErr

RSCU

Undef

Lock Response Error: Indicates that the CS4210 attempted to return a

lock response for a lock request to a serial bus register described in Section

4.4.4 "Autonomous CSR Resources" on page 60, but did not receive an

ack_complete after exhausting all permissible retries.

postedWriteErr

RSCU

Undef

Posted Write Error: Indicates that a host bus error occurred while the

CS4210 was trying to write a 1394 write request, which had already been

given an ack_complete, into system memory. The 1394 destination offset

and sourceID are available in the PostedWriteAddress register described in

Section 3.7.7 "Posted Write Error" on page 29.

isochRx

Undef

Isochronous Receive DMA interrupt: Indicates that one or more isochro-

nous receive contexts have generated an interrupt. This is not a latched

event, it is the OR’ing all bits in (IsochRxIntEvent and IsochRxIntMask). The

IsochRxIntEvent register indicates which contexts have interrupted. See

Section 4.4.16.6 "IsochRxIntEvent Register" on page 74.

isochTx

Undef

Isochronous Transmit DMA interrupt: Indicates that one or more isochro-

nous transmit contexts have generated an interrupt. This is not a latched

event, it is the OR’ing all bits in (isochTxIntEvent and isochTxIntMask). The

isochTxIntEvent register indicates which contexts have interrupted. See

Section 4.4.16.4 "IsochTxIntEvent Register" on page 73.

RSPkt

RSCU

Undef

Receive Response Packet: Indicates that a packet was sent to an asyn-

chronous receive response context buffer and the descriptor’s xferStatus

and resCount fields have been updated. This differs from ARRS (bit 3)

since RSPkt is a per-packet completion indication and ARRS is a per-com-

mand descriptor (buffer) completion indication. AR Response buffers may

contain more than one packet.

RQPkt

RSCU

Undef

Receive Request Packet: Indicates that a packet was sent to an asynchro-

nous receive request context buffer and the descriptor’s xferStatus and res-

Count fields have been updated. This differs from ARRQ (bit 2) since

RQPkt is a per-packet completion indication and ARRQ is a per-command

descriptor (buffer) completion indication. AR Request buffers may contain

more than one packet.

ARRS

RSCU

Undef

Asynchronous Receive Response DMA Interrupt: This bit is condition-

ally set upon completion of an ARDMA Response context command

descriptor.

ARRQ

RSCU

Undef

Asynchronous Receive Request DMA Interrupt: This bit is conditionally

set upon completion of an ARDMA Request context command descriptor.

respTxComplete

RSCU

Undef

Asynchronous Response Transmit DMA Interrupt: This bit is condition-

ally set upon completion of an ATDMA response OUTPUT_LAST* com-

mand.

reqTxComplete

RSCU

Undef

Asynchronous Request Transmit DMA Interrupt: This bit is conditionally

set upon completion of an ATDMA request OUTPUT_LAST* command.

Table 4-26. BAR0+Offset 80h (Set) and 84h (Clear): IntEvent Register (Continued)

Bit

Name

Access

Reset

Description

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