A6986H datasheet(69/71 Pages) STMICROELECTRONICS

69 / 71 page

List of figures

Figure 1.

Application schematic ............................................................... 2

Figure 2.

Pin connection (top view) ............................................................. 3

Figure 3.

Internal block diagram .............................................................. 13

Figure 4.

Internal circuit.................................................................... 14

Figure 5.

Soft-start phase .................................................................. 15

Figure 6.

Soft-start phase with precharged COUT .................................................. 16

Figure 7.

Enable the device with external voltage step............................................... 16

Figure 8.

External soft-start network VSTEP driven ................................................. 18

Figure 9.

External soft-start after UVLO or thermal shutdown .......................................... 18

Figure 10.

Ratiometric startup ................................................................ 19

Figure 11.

Ratiometric startup operation ......................................................... 19

Figure 12.

Output voltage sequencing........................................................... 20

Figure 13.

VOUT = 3.3 V line regulation .......................................................... 21

Figure 14.

VOUT = 3.3 V load regulation ......................................................... 21

Figure 15.

Normalized RDS(on),HS variation ....................................................... 22

Figure 16.

Low noise mode operation ........................................................... 23

Figure 17.

A6986H skip current level transition at ILOAD = 150 mA with L = 10 µH ............................ 24

Figure 18.

Light-load efficiency comparison at different ISKIP - linear scale .................................. 25

Figure 19.

Light-load efficiency comparison at different ISKIP - log scale ................................... 25

Figure 20.

LCM operation with ISKIPH = 600 mA typ. at zero load ....................................... 26

Figure 21.

LCM operation with ISKIPL = 200 mA typ. at zero load........................................ 26

Figure 22.

LCM operation over loading condition (part 1).............................................. 27

Figure 23.

LCM operation over loading condition (part 2-pulse skipping) ................................... 28

Figure 24.

LCM operation over loading condition (part 3-pulse skipping) ................................... 28

Figure 25.

LCM operation over loading condition (part 4-CCM) ......................................... 29

Figure 26.

Quiescent current at VOUT = 3.3 V and zero output load....................................... 29

Figure 27.

Quiescent current at VOUT = 5 V and zero output load ........................................ 30

Figure 28.

Quiescent current at VIN while regulating VOUT = 5 V at zero output load ........................... 30

Figure 29.

Valley current sense operation in overcurrent condition ....................................... 32

Figure 30.

Peak current sense operation in overcurrent condition ........................................ 33

Figure 31.

Output voltage oscillations during heavy short-circuit ......................................... 34

Figure 32.

Zoomed waveforms................................................................ 34

Figure 33.

VBIAS in heavy short-circuit event ...................................................... 35

Figure 34.

Overvoltage operation .............................................................. 36

Figure 35.

Block diagram of the loop............................................................ 37

Figure 36.

Transconductance embedded error amplifier .............................................. 38

Figure 37.

Leading network example ........................................................... 39

Figure 38.

Module plot ..................................................................... 40

Figure 39.

Phase plot ...................................................................... 40

Figure 40.

Magnitude plot for example 2 ......................................................... 41

Figure 41.

Phase plot for example 2 ............................................................ 42

Figure 42.

A6986H application circuit ........................................................... 43

Figure 43.

Voltage supervisor operation ......................................................... 44

Figure 44.

Voltage supervisor operation during OVP ................................................. 45

Figure 45.

Input RMS current................................................................. 46

Figure 46.

Two regulators not synchronized....................................................... 46

Figure 47.

Two regulators synchronized ......................................................... 47

Figure 48.

Synchronization pulse definition ....................................................... 47

Figure 49.

A6986H synchronization driving capability ................................................ 48

Figure 50.

Slave-to-master mode transition ....................................................... 49

A6986H

List of figures

DS12861 - Rev 3

page 69/71

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