A6986H datasheet(22/71 Pages) STMICROELECTRONICS

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5.7

High-side switch resistance vs. input voltage

Figure 15. Normalized RDS(on),HS variation shows the high-side switch RDS(on) variation over the entire input

voltage operating range normalized at the value measured at VIN = 12 V (see Table 5. Electrical characteristics TJ

= - 40 to 135 °C, VIN = 12 V unless otherwise specified.).

Figure 15. Normalized RDS(on),HS variation

-2%

-1%

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

VIN [V]

RDS(on),HS @ I

OUT =1A (normalized @ VIN =12V)

5.8

Light-load operation

The MLF pinstrapping during the power-up phase determines the light-load operation (refer to Table 7. LNM/ LCM

selection (A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. and Table 8. LNM/ LCM

selection (A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.).

5.8.1

Low noise mode (LNM)

The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features

a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed

VIN. The regulator in steady loading condition never skips pulses and it operates in continuous conduction mode

(CCM) over the different loading conditions, thus making this operation mode ideal for noise sensitive

applications.

A6986H

High-side switch resistance vs. input voltage

DS12861 - Rev 3

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A6986H データシート(PDF) 22 Page - STMicroelectronics