© VITESSE SEMICONDUCTOR CORPORATION

Page 5

10/12/98

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8150

2.488Gb/s SONET/SDH

Overhead Monitor

G52186-0, Rev. 3.0

Figure 3: Suggested VSC8150 System Implementation

High Speed Interface

Serial data received on the RXSIN+/- inputs is retimed on the falling edge of RXSCLKIN+/- clock and

appears on the serial loopback output RXSLBOUT+/- (See Figure 11). This interface will pass data at all fre-

quencies from DC to 2.5GHz, and does not necessarily have to retime SONET/SDH data.

Inputs RXSIN+/- and RXSCLKIN+/- do not have internal termination resistors, but internal biasing resis-

tors provide a bias voltage suitable for AC coupling (See Figure 4).

In most situations these inputs will have high transition density and little DC offset. However, in cases

where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same cir-

cuit topology, as shown in figure 4. The reference voltage is created by a resistor divider as shown. If the input

signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-

tered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-

coupling operations, it is recommended that the user provides an external reference voltage which has better

temperature and power supply noise rejection than the on-chip resistor divider. The external reference should

have a nominal value equivalent to the common mode switch point of the DC coupled signal, and can be con-

nected to either side of the differential gate.

B1ERR

SOHOUT[7:0]

SOHCLK

RXFPOUT

VSC8150

FPGA

27x8 Register File

D[7:0]

Q[7:0]

RA[4:0]

WA[4:0]

5 Bit Counter

4 Bit Counter

RESET

RESET

Q[2:0]

Q4

OAM&P

B1 Count

B1 Valid

Frame Count

OH Data

RXSEF

RXLOF

RXFRERR

System Clock

LOS