Application Notes

LMP7711/LMP7712

The LMP7711/LMP7712 are single and dual, low noise, low

offset, rail-to-rail output precision amplifiers with a wide gain

bandwidth product of 17 MHz and low supply current. The

wide

bandwidth

makes

the

LMP7711/LMP7712

ideal

choices for wide-band amplification in portable applications.

The low supply current along with the enable feature that is

built-in on the LMP7711/LMP7712 allows for even more

power efficient designs by turning the device off when not in

use.

The LMP7711/LMP7712 are superior for sensor applica-

tions. The very low input referred voltage noise of only 5.8

nV/

at 1 kHz and very low input referred current noise

of only 10 fA/

mean more signal fidelity and higher

signal-to-noise ratio.

The LMP7711/LMP7712 have a supply voltage range of

1.8V to 5.5V over a wide temperature range of 0˚C to 125˚C.

This is optimal for low voltage commercial applications. For

applications where the ambient temperature might be less

than 0˚C, the LMP7711/LMP7712 are fully operational at

supply voltages of 2.0V to 5.5V over the temperature range

of −40˚C to 125˚C.

The outputs of the LMP7711/LMP7712 swing within 25 mV

of either rail providing maximum dynamic range in applica-

tions requiring low supply voltage. The input common mode

range of the LMP7711/LMP7712 extends to 300 mV below

ground. This feature enables users to utilize this device in

single supply applications.

The use of a very innovative feedback topology has en-

hanced the current drive capability of the LMP7711/

LMP7712, resulting in sourcing currents as much as 47 mA

with a supply voltage of only 1.8V.

The LMP7711 is offered in the space saving TSOT23 pack-

age and the LMP7712 is offered in a 10-pin MSOP. These

small packages are ideal solutions for applications requiring

minimum PC board footprint.

National Semiconductor is heavily committed to precision

amplifiers and the market segments they serves. Technical

support and extensive characterization data is available for

sensitive applications or applications with a constrained error

budget.

CAPACITIVE LOAD

The unity gain follower is the most sensitive configuration to

capacitive loading. The combination of a capacitive load

placed directly on the output of an amplifier along with the

output impedance of the amplifier creates a phase lag which

in turn reduces the phase margin of the amplifier. If phase

margin is significantly reduced, the response will be either

underdamped or the amplifier will oscillate.

The LMP7711/LMP7712 can directly drive capacitive loads

of up to 120 pF without oscillating. To drive heavier capaci-

tive loads, an isolation resistor, R

used. This resistor and C

phase lag or increase the phase margin of the overall sys-

tem. The larger the value of R

voltage will be. However, larger values of R

reduced output swing and reduced output current drive.

INPUT CAPACITANCE

CMOS input stages inherently have low input bias current

and higher input referred voltage noise. The LMP7711/

LMP7712 enhance this performance by having the low input

bias current of only 50 fA, as well as, a very low input

referred voltage noise of 5.8 nV/

. In order to achieve

this a larger input stage has been used. This larger input

stage increases the input capacitance of the LMP7711/

LMP7712. Figure 2 shows typical input common mode input

capacitance of the LMP7711/LMP7712.

This input capacitance will interact with other impedances

such as gain and feedback resistors, which are seen on the

inputs of the amplifier to form a pole. This pole will have little

or no effect on the output of the amplifier at low frequencies

and under DC conditions, but will play a bigger role as the

frequency increases. At higher frequencies, the presence of

this pole will decrease phase margin and also causes gain

peaking. In order to compensate for the input capacitance,

care must be taken in choosing feedback resistors. In addi-

tion to being selective in picking values for the feedback

resistor, a capacitor can be added to the feedback path to

increase stability.

The DC gain of the circuit shown in Figure 3 is simply

−R

20150361

FIGURE 1. Isolating Capacitive Load

20150375

FIGURE 2. Input Common Mode Capacitance

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