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A6986ITR データシート(PDF) 17 Page - STMicroelectronics |
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A6986ITR データシート(HTML) 17 Page - STMicroelectronics |
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17 / 62 page  5.7 Output voltage line regulation All results shown in this section come from measurements performed using the reference schematic depicted in Figure 14. Figure 15. Schematic used for line and load regulation tests Primary output line regulation The regulator features an enhanced primary line regulation due to the peak current mode architecture. Figure 15 shows negligible output voltage variation (normalized to the value measured at VIN = 12 V) over an input voltage range up to 24 V for A6986I with VOUT prim = 5.3 V. Figure 16. Primary line regulation -0.5% -0.4% -0.3% -0.2% -0.1% 0.0% 12 13 14 15 16 17 18 19 20 21 22 23 24 VIN [V] Iout_prim = 0A Iout_prim = 1A A6986I Output voltage line regulation DS13481 - Rev 2 page 17/62 |
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