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L9026 データシート(PDF) 40 Page - STMicroelectronics |
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L9026 データシート(HTML) 40 Page - STMicroelectronics |
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40 / 60 page ![]() 11.4 SPI timing diagram Figure 22. SPI timing diagrams 11.5 SPI frame structure 11.5.1 MOSI frame structure Each MOSI frame has 16 bits with the following structure: • 1 command bit R/W, ‘1’ for write, ‘0’ for read • 5 ADDRESS bits • 8 DATA bits • 1 PARITY bit, odd parity, calculated on bit [2:15] • 1 FR_CNT frame counter bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11.5.2 MISO frame structure Each MISO frame has 16 bits with the following structure: • 1 ERR error bit, ‘1’ if an error happened in the previous transmission, ‘0’ otherwise • 5 ADDRESS bits • 8 DATA bits • 1 PARITY bit, odd parity, calculated on bit [2:15] • 1 FR_CNT frame counter bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L9026 SPI timing diagram DS13397 - Rev 5 page 40/60 |
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