ADMV1011AEZ-R7 datasheet(22/26 Pages) AD

22 / 26 page

ADMV1011

Data Sheet

Rev. A | Page 22 of 26

EVALUATION BOARD INFORMATION

The circuit board used in the application must use RF circuit

design techniques. Signal lines must have 50 Ω impedance, and

the package ground leads and exposed pad must be connected

directly to the ground plane (see Figure 63 and Figure 64). Use a

sufficient number of via holes to connect the top and bottom

ground planes. The evaluation circuit board shown in Figure 65

is available from Analog Devices, upon request.

Layout

Solder the exposed pad on the underside of the ADMV1011 to

a low thermal and electrical impedance ground plane. This pad

is typically soldered to an exposed opening in the solder mask

on the evaluation board. Connect these ground vias to all other

ground layers on the evaluation board to maximize heat

dissipation from the device package. Figure 63 shows the PCB

land pattern footprint for the EVAL-ADMV1011, and Figure 64

shows the solder paste stencil for the EVAL-ADMV1011.

Power-On Sequence

Take the following steps to turn on the EVAL-ADMV1011:

1. Power up VGRF1 andVGRF2 with a −1.8 V supply.

2. Power up VCTL2 and VCTL3 with a −5 V supply for

maximum conversion gain.

3. Power up VDRF1 and VDRF2 with a 5 V supply.

4. Power up VDLO with a 3.5 V supply.

5. Adjust the VGRF1 supply between −1.8 V to −0.8 V until

IDRF1 = 220 mA.

6. Adjust the VGRF2 supply between −1.8 V to −0.8 V until

IDRF2 = 75 mA.

7. Connect LOIN to the LO signal generator with a LO power

between −4 dBm to +4 dBm.

8. For the upper sideband, add a 0 Ω resistor (R1) and

remove the R4 resistor from the board. For the lower

sideband, add a 0 Ω resistor (R4) and remove the R1

resistor from the board.

9. Apply the IF signal to the appropriate port.

Power-Off Sequence

Take the following steps to turn off the EVAL-ADMV1011:

1. Turn off the LO and IF signals.

2. Set VGRF1 and VGRF2 to −1.8 V.

3. Set VCTL2 and VCTL3 to 0 V.

4. Set the VDRF1 and VDRF2 supplies to 0 V and then turn

off the VDRF1 and VDRF2 supplies.

5. Set the VDLO supply to 0 V and then turn off the VDLO

supply.

6. Turn off the VGRF1, VGRF2, VCTL2, and VCTL3 supplies.

2× LO Suppression

The EVAL-ADMV1011 can suppress the 2× LO signal through

the VDI and VDQ test points. The common mode of the two IF

signals is 0 V. Injecting a nonzero voltage at VDI and VDQ can

change the 2× LO level. The 2× LO signal is referenced from the

LOIN pin of the ADMV1011. The VDI and VDQ voltage needs

to be changed iteratively to get the desired level of 2 × LO

suppression. To prevent device malfunction or failure, the

current to the VDI and VDQ test points (IDI and IDQ) must

not source or sink more than 2 mA of current.

ADMV1011AEZ-R7 データシート(PDF) 22 Page - Analog Devices

ADMV1011AEZ-R7 データシート(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

データシートダウンロード