ACE24LA1024A

Two-wire Serial EEPROM

VER 1.3

6

Device Addressing

The 1M EEPROM devices all require an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 4)

The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits

as shown. This is common to all the Serial EEPROM devices.

The 1M EEPROM uses A2 and A1 device address bits to allow as much as eight devices on the same

bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use

an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip

will return to a standby state.

Figure 4: Device Address and two 8-bit data word address

DATA SECURITY: The ACE24LA1024A has a hardware data protection scheme that allows the user to

write protect the entire memory when the WP pin is at VCC.