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PSD312 データシート(PDF) 18 Page - STMicroelectronics |
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PSD312 データシート(HTML) 18 Page - STMicroelectronics |
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18 / 85 page  15 PSD3XX Family 10.0 I/O Port Functions The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications. The next section describes the control registers for the ports. Following that are sections that describe each port. Figures 5 through 7 show the structure of Ports A through C, respectively. Note: any unused input should be connected directly to ground or pulled up to VCC (using a 10K Ω to 100KΩ resistor). 10.1 CSIOPORT Registers Control of the ports is primarily handled through the CSIOPORT registers. There are 24 bytes in the address space, starting at the base address labeled CSIOPORT. Since the PSD3XX uses internal address lines A15-A8 for decoding, the CSIOPORT space will occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to reduce wasted address space by connecting lower order address lines (A7 and below) to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The CSIOPORT space must be defined in your PSDsoft design file. The following tables list the registers located in the CSIOPORT space. 16-Bit Users Note When referring to Table 5B, realize that Ports A and B are still accessible on a byte basis. Note: When accessing Port B on a 16-bit data bus, BHE must be low. Table 5A. CSIOPORT Registers for 8-Bit Data Busses NOTE: 1. ZPSD only. Offset (in hex) Type of from CSIOPORT Access Register Name Base Address Allowed Port A Pin Register +2 Read Port A Direction Register +4 Read/Write Port A Data Register +6 Read/Write Port B Pin Register +3 Read Port B Direction Register +5 Read/Write Port B Data Register +7 Read/Write Power Management Register (Note 1) +10 Read/Write Page Register +18 Read/Write Table 5B. CSIOPORT Registers for 16-Bit Data Busses NOTE: 1. ZPSD only. Offset (in hex) Type of from CSIOPORT Access Register Name Base Address Allowed Port A/B Pin Register +2 Read Port A/B Direction Register +4 Read/Write Port A/B Data Register +6 Read/Write Power Management Register (Note 1) +10 Read/Write Page Register +18 Read/Write |
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