STW8009 datasheet(29/55 Pages) STMICROELECTRONICS

29 / 55 page

STw8009/STw8019

Control registers

29/55

Static phase offset for digital frequency synthesizer (10 bits only)

Under certain circumstances (detailed below), these registers contain the 10 MSBs of the

value with which the phase accumulator of the DDFS is initialized after a 0-to-1 transition of

bit ‘rstosc_buf’ of Reg 2, or after a standard change, or when cyclic phase readjustment has

been programmed (see bits valrst[1:0] of Reg 2). The 14 remaining LSBs loaded into the

accumulator in these cases are all ‘0’s (this allows to define the phase reset value with a

0.35o accuracy).

The procedure to validate the usage of these registers rather than the hard-wired values is

the following:

- Load the registers with the required value

- Set bit ‘selrst’ to 1 (Reg 2)

- Perform a software reset or set ‘rstosc_buf’ to 1 (Reg 2) (to put soft phase value into a

tampon register) and ph_rst_mode[1:0]

Note:

Registers 13-14 are never reset and must be explicitly written into to contain sensible

information.

If bit ‘selrst’=0 (e.g. after a hardware reset) the phase offset used every time the DDFS is re

initialized is a hard-wired value. The hard-wired values being out of any register, they cannot

be read out.

Reset values:

D9C000hex for PAL BDGHI, N, M,

1FC000hex for NTSC-M,

000000hex (blue lines)

REGISTERS 13, 14

Phase_dfs

Address:

0x000D to 0x000E

Type: R/W

register_13

xxx

o23

o22

register_14

o21

o20

o19

o18

o17

o16

o15

o14

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