LP3971 datasheet(17/42 Pages) NSC

17 / 42 page

2C Compatible Interface (Continued)

20180715

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with

the most significant bit (MSB) being transferred first. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte of data has to be followed by an

acknowledge bit. The acknowledge related clock pulse is

generated by the master. The transmitter releases the SDA

line (HIGH) during the acknowledge clock pulse. The re-

ceiver must pull down the SDA line during the 9th clock

pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte

has been received.

After the START condition, a chip address is sent by the I

master. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). The LP3971 address

is 46h. For the eighth bit, a “0” indicates a WRITE and a “1”

indicates a READ. The second byte selects the register to

which the data will be written. The third byte contains data to

write to the selected register.

2C CHIP ADDRESS - 7h’34

MSB

ADR6

Bit7

ADR5

Bit6

ADR4

Bit5

ADR3

Bit4

ADR2

Bit3

ADR1

Bit2

ADR0

Bit1

R/W

Bit0

0110100

R/W

Write Cycle

20180716

When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.

Read Cycle

20180717

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 34h (Chip Address)

LP3971 データシート(PDF) 17 Page - National Semiconductor (TI)

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