AD7450ABRT-R2 datasheet(22/28 Pages) AD

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AD7440/AD7450A

Rev. B | Page 22 of 28

Timing Example 1

Having FSCLK = 18 MHz and a throughput rate of 1 MSPS gives a

cycle time of

1/Throughput = 1/1,000,000 = 1 µs

A cycle consists of

t2 + 12.5(1/FSCLK) + tACQ = 1 µs

Therefore, if t2 = 10 ns

10 ns + 12.5(1/18 MHz) + tACQ = 1 µs

tACQ = 296 ns

This 296 ns satisfies the requirement of 290 ns for tACQ.

From Figure 40, tACQ comprises

2.5(1/FSCLK) + t8 + tQUIET

where t8 = 35 ns. This allows a value of 122 ns for tQUIET,

satisfying the minimum requirement of 60 ns.

Timing Example 2

Having FSCLK = 5 MHz and a throughput rate of 315 kSPS gives a

cycle time of

1/Throughput = 1/315,000 = 3.174 µs

A cycle consists of

t2 + 12.5(1/FSCLK) + tACQ = 3.174 µs

Therefore, if t2 is 10 ns

10 ns + 12.5(1/5 MHz) + tACQ = 3.174 µs

tACQ = 664 ns

This 664 ns satisfies the requirement of 290 ns for tACQ.

From Figure 40, tACQ comprises

2.5(1/FSCLK) + t8 + tQUIET

where t8 = 35 ns. This allows a value of 129 ns for tQUIET,

satisfying the minimum requirement of 60 ns.

As in this example and with other slower clock values, the signal

may already be acquired before the conversion is complete, but

it is still necessary to leave 60 ns minimum tQUIET between

conversions. In Timing Example 2, the signal should be fully

acquired at approximately Point C in Figure 40.

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