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M69KB096AA データシート(PDF) 14 Page - STMicroelectronics

部品番号 M69KB096AA
部品情報  64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM
PDF  48 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M69KB096AA データシート(HTML) 14 Page - STMicroelectronics

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Figure 8. Set Configuration Register (Software Method)
Note: 1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to ‘0001h’ and ‘000h’ respectively.
3. The highest order address location is not modified during this operation.
4. The third write operation must be controlled by the Chip Enable signal.
Figure 9. Read Configuration Register (Software Method)
Note: 1. To read the BCR, RCR on last bus read cycle, DQ0-DQ15 must be set to ‘0001h’, ‘000h’ respectively.
2. The highest order address location is not modified during this operation.
3. The Chip Enable signal, E, must be held High for 150ns before reading the content of the Configuration Register.
4. The third write operation must be controlled by the Chip Enable signal.
Addr.
3FFFFFh
E
G
W
LB, UB
AI10600b
3FFFFFh
3FFFFFh
3FFFFFh
DQ0-DQ15
(2)
CR Data IN
tEHEL2
tEHEL2
tEHEL2
Don't Care
Don't Care
(4)
Addr.
3FFFFFh
E
G
W
LB, UB
AI10601b
3FFFFFh
3FFFFFh
3FFFFFh
DQ0-DQ15
(1)
CR Data
OUT
tEHEL2
tEHEL2
tEHEL2
Don't Care
Don't Care
(3)



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