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M69KB096AA データシート(PDF) 30 Page - STMicroelectronics |
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M69KB096AA データシート(HTML) 30 Page - STMicroelectronics |
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30 / 48 page  M69KB096AA 30/48 Figure 20. LB/UB Controlled, Synchronous Burst Read (4-word) AC Waveforms Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. The Burst Length bits BCR0 to BR2 are set to ‘001’ (4 Words). 3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met. A0-A21 WAIT DQ0-DQ15 K tAVKH tKHKH tKHAX tKHQV1 VALID ADDRESS tKHQX2 tEHQZ tKHEH tLLKH tGLQX tEHEL tELKH tWHKH tKHWX tBLKH tKHBX tGHQZ tAVLH tKHKL READ Burst Identified tKHTX Hi-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT Hi-Z Hi-Z tGLQV AI06785 E G W LB/UB (W = High) tELTV tKHQZ Hi-Z tKHQZ tKHQX1 tKHQZ L tKHLH |
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