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DA9217

High-Performance Dual-Phase DC-DC Converter

Datasheet

Revision 2.0

18-Sep-2020

CFR0011-120-00

26 of 48

Description

CH#_A_VOUT[7:0]

CH# output voltage setting A : CH#_A_VOUT * 10 mV

Setting under 0.3V is clamped to 0.3V, and setting over 1.9V is clamped to 1.9 V

CH#_B_VOUT[7:0]

CH# output voltage setting B : CH#_A_VOUT * 10 mV

Setting under 0.3 V is clamped to 0.3 V, and setting over 1.9V is clamped to 1.9 V

CH#_A_MODE[1:0]

Operation mode selection

0: Force PFM

1: Force PWM. full phase

2: Force PWM with phase shedding

3: Auto mode

CH#_B_MODE[1:0]

Operation mode selection

0: Force PFM

1: Force PWM. full phase

2: Force PWM with phase shedding

3: Auto mode

4.3

Operating Modes

4.3.1

DA9217 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than

VTHR_POR. Once enabled, the host processor can start communicating with DA9217 using the control

interface, after the tIC_EN delay.

4.3.2

OFF

DA9217 is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and

LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.

4.4

I2C Communication

All features of DA9217 can be controlled with the I2C interface which is enabled or disabled in

I2C_EN

Description

I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO

I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data

input/output.

GPIO3 functions as the I2C clock and GPIO4 carries all the power manager bidirectional I2C data.

The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be

pulled high by external pull-up resistors (2

kΩ to 20 kΩ). The standard frequency of the I2C bus is

1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

4.4.1

I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven

towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has

settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the

receiver’s shift register.

A two-byte serial protocol is used containing one byte for address and one byte data. Data and

address transfer are transmitted MSB first for both read and write operations. All transmissions begin

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