DA9220 datasheet(30/62 Pages) DIALOG

30 / 62 page

DA9220

High-Performance Dual-Channel DC-DC Converter

Datasheet

Revision 2.1

17-Sep-2020

CFR0011-120-00

30 of 62

I2C_EN

Description

I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO

I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data

input/output.

GPIO3 functions as the I2C clock and GPIO4 carries all the power manager bidirectional I2C data.

The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be

pulled high by external pull-up resistors (2

kΩ to 20 kΩ). The standard frequency of the I2C bus is

1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

4.4.1

I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven

towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has

settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the

receiver’s shift register.

A two-byte serial protocol is used containing one byte for address and one byte data. Data and

address transfer are transmitted MSB first for both read and write operations. All transmissions begin

with the START condition from the master while the bus is in idle state (the bus is free). It is initiated

by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is

indicated by a low to high transition on the SDA line while the SCL is in the high state).

SCL

SDA

Figure 21: I2C START and STOP Condition Timing

The I2C bus is monitored for a valid slave address whenever the interface is enabled. It responds

immediately when it receives its own slave address. The acknowledge is done by pulling the SDA

line low during the following clock cycle (white blocks marked with A in Figure 22 and Figure 23).

The protocol for a register write from master to slave consists of a START condition, a slave address

with read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a

STOP condition. DA9220 responds to all bytes with acknowledge (A), see Figure 22.

SLAVEadr

REGadr

DATA

S = START condition

A = Acknowledge (low)

P = STOP condition

W = Write (low)

Master to Slave

Slave to Master

7-bits

1-bit

8-bits

Figure 22: I2C Byte Write (SDA Line)

When the host reads data from a register it first has to write to DA9220 with the target register

address and then read from DA9220 with a repeated START, or alternatively a second START,

condition. After receiving the data, the host sends no acknowledge (A*) and terminates the

transmission with a STOP condition, see Figure 23.

DA9220 データシート(PDF) 30 Page - Dialog Semiconductor

DA9220 データシート(HTML) 30 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

データシートダウンロード