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DA9220 データシート(PDF) 35 Page - Dialog Semiconductor

部品番号 DA9220
部品情報  High-Performance Dual-Channel DC-DC Converter
PDF  62 Pages
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メーカー  DIALOG [Dialog Semiconductor]
ホームページ  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

DA9220 データシート(HTML) 35 Page - Dialog Semiconductor

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DA9220
High-Performance Dual-Channel DC-DC Converter
Datasheet
Revision 2.1
17-Sep-2020
CFR0011-120-00
35 of 62
© 2020 Dialog Semiconductor
Table 25: SYS_EVENT_1 (0x0005)
Bit
Symbol
Description
[7]
E_PG2
PG2 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[6]
E_OV2
OV2 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[5]
E_UV2
UV2 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[4]
E_OC2
OC2 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[3]
E_PG1
PG1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[2]
E_OV1
OV1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[1]
E_UV1
UV1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[0]
E_OC1
OC1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
Table 26: SYS_EVENT_2 (0x0006)
Bit
Symbol
Description
[2]
E_GPIO2
GPIO2 event. Writing 1 action clear this bit into 0 if event source
has been released.
[1]
E_GPIO1
GPIO1 event. Writing 1 action clear this bit into 0 if event source
has been released.
[0]
E_GPIO0
GPIO0 event. Writing 1 action clear this bit into 0 if event source
has been released.
Table 27: SYS_MASK_0 (0x0007)
Bit
Symbol
Description
[2]
M_SG
SG IRQ mask
[1]
M_TEMP_CRIT
TEMP_CRIT IRQ mask
[0]
M_TEMP_WARN
TEMP_WARN IRQ mask
Table 28: SYS_MASK_1 (0x0008)
Bit
Symbol
Description
[7]
M_PG2
PG2 event IRQ mask
[6]
M_OV2
OV2 event IRQ mask
[5]
M_UV2
UV2 event IRQ mask
[4]
M_OC2
OC2 event IRQ mask
[3]
M_PG1
PG1 event IRQ mask
[2]
M_OV1
OV1 event IRQ mask
[1]
M_UV1
UV1 event IRQ mask
[0]
M_OC1
OC1 event IRQ mask



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