ADP5065ACBZ-1-R7 datasheet(6/40 Pages) AD

部品番号	ADP5065ACBZ-1-R7

部品情報	Fast Charge Battery Manager with Power Path and USB Compatibility

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メーカー	AD [Analog Devices]

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6 / 40 page

ADP5065

Data Sheet

Rev. D | Page 6 of 40

I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS

Table 3.

Parameter1

Symbol

Min

Typ

Max

Unit

I2C-COMPATIBLE INTERFACE2

Capacitive Load, Each Bus Line

400

SCL Clock Frequency

fSCL

400

kHz

SCL High Time

tHIGH

0.6

µs

SCL Low Time

tLOW

1.3

µs

Data Setup Time

tSUDAT

100

Data Hold Time

tHDDAT

0.9

µs

Setup Time for Repeated Start

tSUSTA

0.6

µs

Hold Time for Start/Repeated Start

tHDSTA

0.6

µs

Bus Free Time Between a Stop and a Start Condition

tBUF

1.3

µs

Setup Time for Stop Condition

tSUSTO

0.6

µs

Rise Time of SCL/SDA

300

Fall Time of SCL/SDA

300

Pulse Width of Suppressed Spike

tSP

Guaranteed by design.

A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2, the I2C timing

diagram.

Timing Diagram

S = START CONDITION

Sr = REPEATED START CONDITION

P = STOP CONDITION

tLOW

tSU,DAT

tHD,DAT

tSU,STA

tSU,STO

tSP

tBUF

tHIGH

SDA

SCL

tHD,STA

Figure 2. I2C Timing Diagram

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