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MPC5121EE データシート(PDF) 21 Page - NXP Semiconductors

部品番号 MPC5121EE
部品情報  MPC5121e (Early) Data Sheet
PDF  86 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
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MPC5121EE データシート(HTML) 21 Page - NXP Semiconductors

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Electrical and Thermal Characteristics
MPC5121e (Early) Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
2.1.5
Power Dissipation
Power dissipation of the MPC5121e is caused by 4 different components: the dissipation of the internal or core digital logic
(supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD),
the dissipation of the IO logic (supplied by VDD_MEM_IO and VDD_IO) and the dissipation of the PHYs (supplied by own
supplies). Table 7 details typical measured core and analog power dissipation figures for a range of operating modes. However,
the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each application case
using the following formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f
is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the
MPC5121e processor must not exceed the value, which would cause the maximum junction temperature to be exceeded.
Eqn. 2
2.1.6
Thermal Characteristics
Table 7. Power Dissipation
Core Power Supply (VDD_CORE)
SpecID
Mode
High-Performance
Unit
e300 = 300 MHz, CSB = 200 MHz
Operational1,
1 Typical core power is measured at VDD_CORE = 1.4 V, Tj = 25 C.
800
mW
D5.1
Deep-Sleep1,
1mW
D5.2
Hibernation
20
uW
D5.3
PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
Typical
25
mW
D5.4
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO)
Typical
300
mW
D5.5
PHY Power Supplies (USB_VDDA, SATA_VDDA)
Typical
200
mW
D5.6
Table 8. Thermal Resistance Data
Rating
Board Layers
Sym
Value
Unit
SpecID
Junction to Ambient Natural
Convection1,2
Single layer board (1s)
RθJA
30
°C/W
D6.1
Junction to Ambient Natural
Convection1,3
Four layer board (2s2p)
RθJMA
22
°C/W
D6.2
P
IO
P
IOint
N
M
∑
+
CVDD_IO
2
f
×
×
×
=
P
total
P
core
P
analog
P
IO
PPHYs
++
+
=



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