MPC5121EE datasheet(68/86 Pages) NXP

68 / 86 page

MPC5121e (Early) Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 47. Timing Diagram – IrDA Transmit Line

2.3.20.4

SPI Mode

NOTE

Output timing is specified at a nominal 50 pF load.

Table 44. Timing Specifications – SPI Master Mode, Format 0 (CPHA = 0)

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A20.26

SCK pulse width, 50% SCK duty cycle

15.0

—

A20.27

Slave select clock delay, programable in the PSC CCS register

30.0

—

A20.28

Output Data valid after Slave Select (SS)

—

8.9

A20.29

Output Data valid after SCK

—

8.9

A20.30

Input Data setup time

6.0

—

A20.31

Input Data hold time

1.0

—

A20.32

Slave disable lag time

—

TSCK

A20.33

Sequential Transfer delay, programable in the PSC CTUR / CTLR

15.0

—

A20.34

Clock falling time

—

7.9

A20.35

Clock rising time

—

7.9

A20.36

IrDA_TX

(SIR/FIR/MIR)

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