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MCIMX503CVM8B データシート(PDF) 69 Page - NXP Semiconductors |
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MCIMX503CVM8B データシート(HTML) 69 Page - NXP Semiconductors |
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69 / 136 page  Electrical Characteristics i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 69 4.8.1 DRAM Command & Address Output Timing—DDR2 and LPDDR1 The following diagrams and tables specify the timings related to the address and command pins, which interfaces DDR2 and LPDDR1 memory devices. Table 45. EMI Command/Address AC Timing ID Description Symbol Min Max Unit DDR1 CK cycle time tCK 3.75 — ns DDR2 CK high level width tCH 0.48 tCK 0.52 tCK ns DDR3 CK low level width tCL 0.48 tCK 0.52 tCK ns DDR4 Address and control output setup time tIS 0.5 tCK - 0.3 —ns DDR5 Address and control output hold time tIH 0.5 tCK - 0.3 —ns Figure 28. DRAM Command/Address Output Timing—DDR2 and LPDDR1 DRAM_SDCLK DRAM_SDCLK_B DRAM_CS0 DRAM_RAS DRAM_CAS DRAM_SDWE bank row bank column DRAM_ADDR DDR1 DDR2 DDR3 DDR4 DDR5 DDR4 DDR5 DDR4 DDR5 |
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