VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8166

2.488 Gbit/sec

1:16 SONET/SDH Demux with Clock Recovery

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

G52252-0, Rev 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/9/99

AC Characteristics

Figure 6: AC Timing Waveforms

Figure 7: Differential and Single Ended Input and Output Voltage Measurement

VALID DATA (1)

VALID DATA (2)

D0

D1 D2

D3

D4

D5 D6

D7

D8

D9 D10 D11 D12 D13 D14 D15

Parallel data clock output

Parallel data outputs

Parallel data clock output

High speed differential serial data input

CLK16O+

D(0...15)+

CLK32O+

DI+

Single

Ended

Swing

Differential

Swing

=

α

=

α

a

a

b

b

* Differential swing

(α) is specified as | b - a | (or | a - b |), as is the single ended swing.

Differential swing is specified as equal in magnitude to single ended swing.