© VITESSE SEMICONDUCTOR CORPORATION

Page 13

11/9/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8166

2.488 Gbit/sec

1:16 SONET/SDH Demux with Clock Recovery

G52252-0, Rev. 3.0

Package Information

NOTES:

128 PQFP Package Drawings

Package #: 101-322-5

Issue #: 2

STANDOFF

LEAD COPLANARITY

MAX.

0.17

.25

A

L

A1

A1

A2

R1

R

θ

b

e

A

10

° TYP.

10

° TYP.

TOP VIEW

EXPOSED

HEATSINK

EXPOSED

INTRUSION

0.127 MAX.

RAD. 2.92

± .50

(2)

2.54

± .50

PIN 128

PIN 1

E1

E

D1

D

Notes: 1)

Drawing is not to scale

2)

All dimensions in mm

3)

Package represented is

also used for the 64,

80, & 100 PQFP packages.

Pin count drawn does

not reflect the 128 Package.

PIN 38

PIN 64

PIN 102

Key

mm

Tolerance

A2.35

MAX

A1

0.25

MAX

A2

2.00

+.10

D

17.20

±.20

D1

14.00

±.10

E

23.20

±.20

E1

20.00

±.10

L

.88

+.15/-.10

e.50

BASIC

b

.22

±.05

θ

0°-7°

R.30

TYP

R1

.20

TYP