SPC572L64F2 datasheet(30/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

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DocID027866 Rev 5

Table 15. MEDIUM configuration output buffer electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

ROH_M

PMOS output impedance

MEDIUM configuration

4.5 V < VDD_HV_IO < 5.5 V

Push pull, IOH < 2 mA

120

200

260

ROL_M

NMOS output impedance

MEDIUM configuration

4.5 V < VDD_HV_IO < 5.5 V

Push pull, IOL < 2 mA

120

200

260

fMAX_M

Output frequency

MEDIUM configuration

CL =25 pF(3)

——

MHz

CL =50 pF(3)

——

DCL = 200 pF(3)

——

1.5

tTR_M

Transition time output pin

MEDIUM configuration(4)

CL = 25 pF

4.5 V < VDD_HV_IO < 5.5 V

—

CL =50 pF

4.5 V < VDD_HV_IO < 5.5 V

—

DCL = 200 pF

4.5 V < VDD_HV_IO < 5.5 V

—

200

CL = 25 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

—

CL = 50 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

—

CL = 200 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

—

300

|tSKEW_M| CC

Difference between rise and

fall time

——

—

IDCMAX_M CC

Maximum DC current

—

TPHL/PLH CC

Propagation delay

CL = 25 pF,

4.5 V < VDD_HV_IO < 5.9 V

—

CL = 25 pF,

3.0 V < VDD_HV_IO < 3.6 V

——

CL = 50 pF,

4.5 V < VDD_HV_IO < 5.9 V

——

CL = 50 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

——

1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0

2. All values need to be confirmed during device validation.

3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added to

calculate total signal capacitance (CTOT = CL + CIN).

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