SPC572L64F2 datasheet(39/112 Pages) STMICROELECTRONICS

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SPC572Lx

Electrical characteristics

111

Note:

No restrictions exist on reset signal slew rate apart from absolute maximum rating

compliance.

3.11

Oscillator and PLL

Single phase-locked loop (PLL) module with the reference PLL (PLL0) generating the system

and auxiliary clocks from the main oscillator driver.

IOL_R

C Strong pull-down current(1)

Device under power-on

reset

VDD_HV_IO = VDD_POR,

VOL = 0.35 * VDD_HV_IO

0.2

—

——

—

Device under power-on

reset

3.0 V < VDD_HV_IO <5.5 V,

VOL >1.0 V

—

|IWPU|

P Weak pull-up current absolute

value

ESR0 pin

VIN = 0.69 * VDD_HV_IO

—

µA

ESR0 pin

VIN = 0.49 * VDD_HV_IO

——

|IWPD|

P Weak pull-down current

absolute value

PORST pin

VIN = 0.69 * VDD_HV_IO

—

130

µA

PORST pin

VIN = 0.49 * VDD_HV_IO

—

WFRST

P PORST and ESR0 input

filtered pulse

—

500

WNFRST SR

P PORST and ESR0 input not

filtered pulse

—2000

—

WFNMI

P ESR1 input filtered pulse

—

WNFNMI SR

P ESR1 input not filtered pulse

—

400

—

1. IOL_R applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active on

PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.

Table 19. Reset electrical characteristics (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

PORST must be connected to an external power-on supply circuitry. Minimum requested

circuitry is external pull-up to ensure device can exit reset.

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