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STM32WB50CG データシート(PDF) 30 Page - STMicroelectronics |
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STM32WB50CG データシート(HTML) 30 Page - STMicroelectronics |
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30 / 119 page  Table 6. STM32WB50CG and STM32WB30CE modes overview Mode Regulator CPU1 Flash SRAM Clocks DMA and peripherals Wakeup source Consumption(1) Wakeup time Run MR Yes ON(2) ON Any All N/A 107 µA/MHz N/A LPRun LPR Yes ON(2) ON Any except PLL All except RF, RNG N/A 103 µA/MHz 15.33 µs Sleep MR No ON(2) ON(3) Any All Any interrupt or event 41 µA/MHz 9 cycles LPSleep LPR No ON(2) ON(3) Any except PLL All except RF, RNG Any interrupt or event 45 µA/MHz 9 cycles Stop 0 MR No OFF ON LSE, LSI, HSE(4), HSI16(5) RF, BOR, PVD RTC, IWDG USART1(6) I2C1(7) LPTIMx (x=1, 2) All other peripherals are frozen. Reset pin, all I/Os, RF, BOR, PVD RTC, IWDG USART1 I2C1 LPTIMx (x=1, 2) 105 µA 1.7 µs Stop 1 LPR No OFF ON LSE, LSI, HSE(4), HSI16(5) RF, BOR, PVD RTC, IWDG USART1(6) I2C1(7) LPTIMx (x=1, 2) All other peripherals are frozen. Reset pin, all I/Os RF, BOR, PVD RTC, IWDG USART1 I2C1 LPTIMx (x=1, 2) 9.25 µA w/o RTC 9.45 µA w RTC 4.7 µs Stop 2 LPR No OFF ON LSE, LSI RF, BOR, PVD RTC, IWDG LPTIM1 All other peripherals are frozen. Reset pin, all I/Os RF, BOR, PVD RTC, IWDG LPTIM1 1.85 µA w/o RTC 2.25 µA w RTC 5.71 µs |
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