ATAR080 datasheet(36/68 Pages) ATMEL

36 / 68 page

ATAR080

4675D–4BMCU–12/04

Timer 2 Output Mode 5

Manchester Modulator: Timer 2 modulates the SSI internal data output (SO) to

Manchester code.

Figure 40. Manchester Modulation

Timer 2 Output Mode 7

PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O).

In this mode the timer overflow defines the period and the compare register defines the

duty cycle. During one period only the first compare match occurrence is used to toggle

the timer output flip-flop, until overflow occurs all further compare match are ignored.

This avoids the situation that changing the compare register causes the occurrence of

several compare match during one period. The resolution at the pulse-width modulation

Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit.

Figure 41. PWM Modulation

TOG2

T2O

010

8-bit SR Data

Bit 7

Bit 0

Bit 7

Bit 0

Data: 00110101

255

100

255 0

150

255 0 50

255 0

100

T2R

Input clock

Counter 2/2

OVF2

CM2

INT4

T2O

load the next

compare value

T2CO2 = 150

load

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