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R7FA4M2AB3CFL データシート(PDF) 36 Page - Renesas Technology Corp |
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R7FA4M2AB3CFL データシート(HTML) 36 Page - Renesas Technology Corp |
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36 / 92 page  Sub-clock oscillator output SOSCCR.SOSTP Sub-clock tSUBOSCWT Figure 2.11 Sub-clock oscillation start timing 2.3.3 Reset Timing Table 2.19 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width Power-on tRESWP 0.7 — — ms Figure 2.12 Deep Software Standby mode tRESWD 0.6 — — ms Figure 2.13 Software Standby mode, Subosc-speed mode tRESWS 0.3 — — ms All other tRESW 200 — — µs Wait time after RES cancellation tRESWT — 37.3 41.2 µs Figure 2.12 Wait time after internal reset cancellation (IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error reset, bus master MPU error reset, TrustZone error reset) tRESW2 — 324 397.7 µs — VCC RES Internal reset signal (low is valid) tRESWP tRESWT VCCmin Figure 2.12 RES pin input timing under the condition that VCC exceeds VPOR voltage threshold RES Internal reset signal (low is valid) tRESWD, tRESWS, tRESW tRESWT Figure 2.13 Reset input timing RA4M2 Datasheet 2. Electrical Characteristics R01DS0367EJ0110 Rev.1.10 Jan 27, 2021 Page 36 of 92 |
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