RZSLASHT2M datasheet(5/127 Pages) RENESAS

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Table 1.7

Timers (2 of 2)

Feature

Functional description

General PWM timer (GPT)

● 32 bits × 18 channels

● Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all

channels

● Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 400 MHz for LLPP)

● 2 input/output pins per channel

● 2 output compare/input capture registers per channel

● For the 2 output compare/input capture registers of each channel, 4 registers are provided

as buffer registers and are capable of operating as comparison registers when buffering is

not in use.

● In output compare operation, buffer switching can be at peaks or troughs, enabling the

generation of laterally asymmetrically PWM waveforms.

● Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

● Synchronizable operation of the several counters

● Modes of synchronized operation (synchronized, or displaced by desired times for phase

shifting)

● Generation of dead times in PWM operation

● Through combination of 3 counters, generation of automatic 3-phase PWM waveforms

incorporating dead times

● Starting, clearing, stopping, switching, up/down counters, and input capture in response to

external or internal triggers

● Starting, clearing, stopping, switching, up/down counters, and input capture in response to

input level comparison

● Internal trigger sources: software and compare-match

● Generation of triggers for A/D converter conversion

● Digital noise filter function for signals on the input capture and external trigger pins

● Event linking by the ELC

Compare match timer (CMT)

● (16 bits × 2 channels) × 3 units

● Select from among four counter-input clock signals for each channel

Compare match timer W (CMTW)

● (32 bits × 1 channel) × 2 units

● Compare-match, input-capture input, and output-comparison output are available.

● Select from among four counter-input clock signals for each channel

● Interrupt requests can be output in response to compare-match, input-capture, and output-

comparison events.

Watchdog timer (WDT)

● 14 bits × 2 channels

● Select from among six counter-input clock signals for each channel

Port output enable 3 (POE3)

● Control of the high-impedance state of the MTU3 waveform output pins

● 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#

● Initiation on detection of short-circuited outputs (detection of simultaneous PWM output to

the active level)

● Initiation by input clock oscillation-stoppage detection, PLL oscillation anomaly detection,

DSMIF error detection, or software

● Additional programming of output control target pins is enabled

Port output enable for GPT (POEG)

● Controlling the output disable for GPT waveform output

● Initiation by input level detection of GTETRG pins

● Initiation by output disable request from GPT

● Initiation by detection of oscillation stop, DSMIF error detection, or by software

Real time clock (RTC)

● A 100 year calendar from 2000 to 2099

● BCD code display

● Clock source is division of main oscillator.

● Automatic adjustment function for leap years

RZ/T2M Datasheet

1. Overview

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

Page 5 of 127

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