LSM6DSTX datasheet(73/175 Pages) STMICROELECTRONICS

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9.40

FIFO_STATUS2 (3Bh)

FIFO status register 2 (R)

Table 112. FIFO_STATUS2 register

FIFO_

WTM_IA

FIFO_

OVR_IA

FIFO_

FULL_IA

COUNTER_

BDR_IA

FIFO_OVR_

LATCHED

DIFF_

FIFO_9

DIFF_

FIFO_8

Table 113. FIFO_STATUS2 register description

FIFO_WTM_IA

FIFO watermark status. Default value: 0

(0: FIFO filling is lower than WTM;

1: FIFO filling is equal to or greater than WTM)

Watermark is set through bits WTM[7:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h).

FIFO_OVR_IA

FIFO overrun status. Default value: 0

(0: FIFO is not completely filled; 1: FIFO is completely filled)

FIFO_FULL_IA

Smart FIFO full status. Default value: 0

(0: FIFO is not full; 1: FIFO will be full at the next ODR)

COUNTER_BDR_IA

Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and

COUNTER_BDR_REG2 (0Ch). Default value: 0

This bit is reset when these registers are read.

FIFO_OVR_LATCHED

Latched FIFO overrun status. Default value: 0

This bit is reset when this register is read.

DIFF_FIFO_[9:8]

Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00

In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)

9.41

TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3

(43h)

Timestamp first data output register (R). The value is expressed as a 32-bit word and the bit resolution is 25 µs.

Table 114. TIMESTAMP output registers

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Table 115. TIMESTAMP output register description

D[31:0]

Timestamp output registers: 1LSB = 25 µs

LSM6DSTX

FIFO_STATUS2 (3Bh)

DS14039 - Rev 1

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