ST7293C3B6 datasheet(18/69 Pages) STMICROELECTRONICS

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ST7294

3.5 WATCHDOG SYSTEM

The Watchdog System consists in a divide-by-8

counter and a fixed divide-by-1024 prescaler. It is

controlled through bit WDOG of the Miscellaneous

The Watchdog Enable mode mask option selects

the state of the Watchdog System after an exter-

nal or a power-on reset. In the “programmable en-

able” option, a reset causes the watchdog to be

disabled and the counter to be forced to zero.

When the watchdog is configured with the “pro-

grammable enable” option, the watchdog system

is enabled by setting the WDOG bit of the Miscel-

laneous Register (0Ch). Only an external or a

power-on reset can clear WDOG and disable the

watchdog system.

Whatever the option, when the watchdog counter

is enabled, it is driven by the CPU clock through

the divide-by-1024 prescaler (i.e. the counter

clock period is 1024 CPU clock cycles). It is reset

to zero by writing WDOG at 1. A system reset is

generated if the counter reaches it maximum

count (8). To avoid a system reset, the software

must therefore reset the counter at least after a

timer tDOG from the last clear or from the time the

watchdog system has been enabled.

Care has to be taken when enabling the counter

(“programmable enable” option only). The pres-

caler is actually in an unknown state at the time

WDOG is set. The first rising edge can thus be

sent to the watchdog counter after a time com-

prised between 0 and 1024 CPU clock cycles. In

this mode, the first reset of the watchdog counter

should therefore not occur later than 6x1024 CPU

clock cycles after it has been enabled.

The system reset is generated by pulling down the

RESET pin for at least one and a half CPU clock

cycle. The state of the RESET pin is re-entered,

thus causing an external reset to be issued.

The WATCHDOG DURING WAIT mask option al-

lows to determine the watchdog function during

the WAIT low power mode. In the “active during

WAIT” option, the watchdog is kept active, thus

able to reset the MCU if it remains in WAIT mode

longer than the watchdog timeout period. In the

“suspended during WAIT” option, it suspends op-

eration during the WAIT mode and resets its coun-

ter. It will then resume operation when exiting the

WAIT mode.

The HALT mode is inhibited when the watchdog

system is enabled. However if a HALT instruction

is executed while it is enabled, a watchdog reset is

immediately generated.

Figure 13. Watchdog Block Diagram

8th State Decoder

÷ 8 Watchdog Counter

Control Logic

Latch

Reset

Schmitt Trigger

Miscellaneus

Internal

CPU Clock

÷ 1024

Power ON

VR02048

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