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Revision 1.19

8 - 15

AS1150, AS1151

Data Sheet

Pin Assignments

7 Pinout

Pin Assignments

Figure 15. Pin Assignments (Top View)

Pin Descriptions

Table 4. Pin Descriptions

Pin Number

Pin Name

Description

1IN1-

Inverting Differential Receiver Input

2IN1+

Noninverting Differential Receiver Input

3IN2+

Noninverting Differential Receiver Input

4IN2-

Inverting Differential Receiver Input

5IN3-

Inverting Differential Receiver Input

6IN3+

Noninverting Differential Receiver Input

7IN4+

Noninverting Differential Receiver Input

8IN4-

Inverting Differential Receiver Input

9ENn

Receiver Enable Input. Internally pulled down to GND.

When EN = high and ENn = low or open, the receiver outputs are active. For other

combinations of EN and ENn, the outputs are disabled and in high impedance.

10

OUT4

LVCMOS/LVTTL Receiver Output

11

OUT3

LVCMOS/LVTTL Receiver Output

12

GND

Ground

13

capacitors.

14

OUT2

LVCMOS/LVTTL Receiver Output

15

OUT1

LVCMOS/LVTTL Receiver Output

16

EN

Receiver Enable Input. Internally pulled down to GND.

When EN = high and ENn = low or open, the receiver outputs are active. For other

combinations of EN and ENn, the outputs are disabled and in high impedance.

AS1150

AS1151

1

IN1-

2

IN1+

3

IN2+

4

IN2-

5

IN3-

6

IN3+

7

IN4+

8

IN4-

16 EN

15 OUT1

14 OUT2

12 GND

11 OUT3

10 OUT4

9

ENn