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FT812Q-R データシート(PDF) 26 Page - Bridgetek Pte Ltd. |
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FT812Q-R データシート(HTML) 26 Page - Bridgetek Pte Ltd. |
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26 / 63 page  Copyright © Bridgetek Pte Ltd 26 FT81X Embedded Video Engine Datasheet Version 1.4 Document No.: BRT_000002 Clearance No.: BRT#004 Font Index => 16/ 18 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 116 t 8 4 4 5 6 8 9 6 7 8 9 11 14 17 23 29 117 u 8 5 7 9 10 14 18 8 9 12 14 17 24 31 41 52 118 v 8 6 7 8 10 13 16 7 9 11 12 16 21 27 36 46 119 w 8 8 10 12 14 18 23 11 13 16 18 23 32 41 54 70 120 x 8 6 7 8 10 12 16 7 9 11 12 16 21 27 36 46 121 y 8 5 7 8 10 13 16 7 9 11 12 16 21 27 36 46 122 z 8 5 7 8 9 12 16 8 9 11 12 15 22 27 36 46 123 { 8 3 5 6 6 8 11 5 6 8 8 11 15 18 24 31 124 | 8 3 3 4 5 6 9 3 4 5 6 7 10 14 18 23 125 } 8 3 5 6 6 8 11 5 6 7 9 10 15 18 24 31 126 ~ 8 7 8 10 10 14 19 10 11 14 15 21 29 36 47 63 127 DEL 8 0 0 0 0 0 0 3 4 5 6 5 10 13 18 23 Table 4-9 ROM font ASCII character width in pixels 128 Ç 144 É 160 á 176 ░ 192 └ 208 ╨ 224 α 240 Ξ 129 ü 145 æ 161 í 177 ▒ 193 ┴ 209 ╤ 225 ß 241 ± 130 é 146 Æ 162 ó 178 ▓ 194 ┬ 210 ╥ 226 Γ 242 ≥ 131 â 147 ô 163 ú 179 │ 195 ├ 211 ╙ 227 ∏ 243 ≤ 132 ä 148 ö 164 ñ 180 ┤ 196 ─ 212 ╘ 228 Σ 244 ⌠ 133 à 149 ò 165 Ñ 181 ╡ 197 ┼ 213 ╒ 229 σ 245 ⌡ 134 å 150 û 166 ª 182 ╢ 198 ╞ 214 ╓ 230 µ 246 ÷ 135 ç 151 ù 167 º 183 ╖ 199 ╟ 215 ╫ 231 τ 247 ≈ 136 ê 152 ÿ 168 ¿ 184 ╕ 200 ╚ 216 ╪ 232 Φ 248 ° 137 ë 153 Ö 169 ⌐ 185 ╣ 201 ╔ 217 ┘ 233 θ 249 • 138 è 154 Ü 170 ¬ 186 ║ 202 ╩ 218 ┌ 234 Ω 250 · 139 ï 155 ₵ 171 ½ 187 ╗ 203 ╦ 219 █ 235 δ 251 √ 140 î 156 £ 172 ¼ 188 ╝ 204 ╠ 220 ▄ 236 ω 252 ⁿ 141 ì 157 ¥ 173 ¡ 189 ╜ 205 ═ 221 ▌ 237 φ 253 ² 142 Ä 158 Pt 174 « 190 ╛ 206 ╬ 222 ▐ 238 Ɛ 254 ■ 143 Å 159 ƒ 175 » 191 ┐ 207 ╧ 223 ▀ 239 Π 255 nbsp Table 4-10 ROM font Extended ASCII characters Note: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters. Note: All fonts included in the FT81x ROM are widely available to the market-place for general usage. See section nine for specific copyright data and links to the corresponding license agreements. 4.4 Parallel RGB Interface The RGB parallel interface consists of 23 or 29 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 or 8 signals each for R, G and B. A set of RGB registers configure the LCD operation and timing parameters. REG_PCLK is the PCLK divisor. The default value is 0, which means the PCLK output is disabled. When REG_PCLK is none 0 (1-1023), the PCLK frequency can be calculated as: |
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