MIC2133 datasheet(22/50 Pages) MICROCHIP

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DS20006653B-page 22

MIC2133

Calculate CINJ using the following equation.

EQUATION 4-12:

Using too low a CINJ may result in oscillations at the

beginning of the soft start. These oscillations can be

reduced either by using a higher CINJ or COUT by

reducing the feedback ripple.

4.5

Detailed Device Description

4.5.1

CURRENT BALANCING BETWEEN

PHASES

One important benefit of the two-phase operation is the

thermal advantage gained by distributing the heat over

multiple devices and a greater PCB area. By doing this,

the system designer avoids the complexity of driving

parallel MOSFETs and the expense of using expensive

heatsinks.

To accomplish the thermal advantage, it is important

that each phase carries the same amount of current at

any load level. In the MIC2133, both phase currents are

sensed across a low-side MOSFET, RDS(ON), during

off-time. The low-side MOSFET current is tracked

during off-time and held close to peak value in the val-

ley point. The average current information is generated

by summing all the phases’ sensed currents and divid-

ing by the number of phases (two for two phases). An

error current per phase is generated by making the dif-

ference between the average current information and

each phase current, which is used to modulate TON1

and TON2 to cancel the error in the current sharing.

FIGURE 4-6:

MIC2133 Current Sharing

Circuit.

4.5.2

HyperLight Load (HLL) MODE

The

MIC2133

always

operates

Continuous

Conduction Mode (CCM) and both phases support the

load current equally at high loads. To operate the system

at a higher efficiency, the MIC2133 will shed the Phase 2

when the load current drops below the programmed

threshold level, below the full load current value. In CCM

mode, the inductor current can go negative at light loads.

However, at light loads, the MIC2133 is able to force the

inductor current to operate in Discontinuous Conduction

Mode (DCM) when it operates in HLL mode. In HLL

mode, the efficiency is optimized by shutting down all the

non-essential circuits and minimizing the supply current.

The MIC2133 wakes up and turns on the high-side

MOSFET when the Feedback Voltage, VFBS, drops and

Vgm is below VREF_COM (1.2V).

The MIC2133 has a Zero-Crossing (ZC Detection)

comparator that monitors the inductor current by sens-

ing the voltage drop across the low-side MOSFET

during its on-time. If Vgm > VREF_COM and the inductor

current goes slightly negative, the MIC2133 automati-

cally powers down most of the IC circuitry and goes into

a Low-Power mode.

Once the MIC2133 goes into DCM mode, both the

high-side and low-side MOSFETs are kept in the OFF

state. Then, the load current is supplied by the output

capacitors and VOUT drops. If the load current is suffi-

ciently large, the drop of VOUT causes VFBS to drop and

Vgm to go below VREF_COM (1.2V), and the high-side

MOSFET is turned on for TON. Then, at the end of the

TON period, the low-side MOSFET is turned on for TOFF

until the next TON starts because the inductor current

during the low-side MOSFET on-time is larger than

zero. Then, the cycle repeats and all the circuits

wake-up into normal CCM mode. The following figure

shows the control loop timing in DCM mode.

During DCM mode, the bias current of most circuits is

reduced. As a result, the total power supply current

during DCM mode is only about 400 µA, allowing the

MIC2133 to achieve high efficiency in light load appli-

cations.

CINJ

CFF

ESRCOUT





fCO L



-------------------------------------



VOUT

5V 100 ns



fSW



-------------------------------------------



SW1

CSN1

VIN

DL1

DH1

MIC2133

SW2

CSN2

VIN

DL2

DH2

CSP1

CSP2

TON1

GENERATOR

CSH

DROOP

SAMPLE TRACK

& HOLD

SAMPLE TRACK

& HOLD

1.2V

0.5

CONTROL

LOGIC

TON2

GENERATOR

OUTS

ITON1

ITON2

PHASE1

DRIVER

CONTROL

LOGIC

PHASE2

DRIVER

CONTROL

LOGIC

ADAPTABLE

TON

CONTROL

FREQ

VIN

ITON2

VOUT

OUTS

+120mV

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