5

Instructions

5.1

Write operations

Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The

device acknowledges this, as shown in Figure 6, and waits for the address byte. The device responds to each

address byte with an acknowledge bit, and then waits for the data byte.

Table 3. Address byte

A7

A6

A5

A4

A3

A2

A1

A0

When the bus master generates a stop condition immediately after a data byte Ack bit (in the "10th bit" time slot),

either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any

other time slot does not trigger the internal write cycle.

After the stop condition and the successful completion of an internal write cycle (tW), the device internal address

counter is automatically incremented to point to the next byte after the last modified byte.

During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any

requests.

If the write control input (WC) is driven high, the Write instruction is not executed and the accompanying data

bytes are not acknowledged , as shown in Figure 7.

M24C16-W M24C16-R M24C16-F

Instructions

DS9194 - Rev 11

page 8/40