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ST20-GP6 データシート(PDF) 41 Page - STMicroelectronics |
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ST20-GP6 データシート(HTML) 41 Page - STMicroelectronics |
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41 / 123 page ![]() ST20-GP6 41/123 7.2 Instruction characteristics Table 7.3 gives the basic function code of each of the primary instructions. Where the operand is less than 16, a single byte encodes the complete instruction. If the operand is greater than 15, one prefix instruction ( pfix) is required for each additional four bits of the operand. If the operand is neg- ative the first prefix instruction will be nfix. Examples of pfix and nfix coding are given in Table 7.1. Any instruction which is not in the instruction set tables is an invalid instruction and is flagged ille- gal, returning an error code to the trap handler, if loaded and enabled. The Notes column of the tables indicates the features of an instruction as described in Table 7.2. Mnemonic Function code Memory code ldc #3 #4 #43 ldc #35 is coded as pfix #3 #2 #23 ldc #5 #4 #45 ldc #987 is coded as pfix #9 #2 #29 pfix #8 #2 #28 ldc #7 #4 #47 ldc -31 ( ldc #FFFFFFE1) is coded as nfix #1 #6 #61 ldc #1 #4 #41 Table 7.1 Prefix coding Ident Feature E Instruction can set an IntegerError trap L Instruction can cause a LoadTrap trap S Instruction can cause a StoreTrap trap O Instruction can cause an Overflow trap I Interruptible instruction A Instruction can be aborted and later restarted. D Instruction can deschedule T Instruction can timeslice Table 7.2 Instruction features |
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