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STM32H7B0IB データシート(PDF) 126 Page - STMicroelectronics

部品番号 STM32H7B0IB
部品情報  32-bit Arm® Cortex®-M7 280 MHz MCUs, 128-Kbyte Flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  205 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B0IB データシート(HTML) 126 Page - STMicroelectronics

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Symbol
Parameter
Conditions
Min(1)
Typ(1)
Max(1)(2)
Unit
thr(OUT)
thf(OUT)
Data output hold time
DHQC = 1, PRESCALER[7:0]=1,2...
t(CLK)/4
ns
-
-
1. Guaranteed by characterization results, unless otherwise specified.
2. At VOS1, these values are degraded by up to 5 %.
3. The maximum frequency values are given for a maximum RWDS to DQ skew ≤ ±1.0 ns.
4. DHQC must be set to reach the mentioned frequency.
5. Guaranteed by design.
6. Using PC2, PC3, PI11, PF0 or PF1 I/Os limits the maximum clock frequency.
7. Delay block bypassed.
8. Using PC2, PC3, PI11, PF0 or PF1 I/O in the data bus adds 3.5 ns to this timing value.
Figure 41. OctoSPI timing diagram - DTR mode
Data output
D0
D2
D4
Clock
Data input
D0
D2
D4
t(CLK)
tw(CLKH)
tw(CLKL)
tr(CLK)
tf(CLK)
tsf(IN) thf(IN)
tvf(OUT)
thr(OUT)
D1
D3
D5
D1
D3
D5
tvr(OUT)
thf(OUT)
tsr(IN)thr(IN)
Figure 42. OctoSPI Hyperbus clock
CLK
t(NCLK)
tw(NCLKL)
tw(NCLKH)
tf(NCLK)
tr(NCLK)
tr(CLK)
tw(CLKH)
tw(CLKL)
t(CLK)
tf(CLK)
NCLK
VOD(CLK)
Figure 43. OctoSPI Hyperbus read
NCS
tACC= Initial access
Latency count
Command address
47:40 39:32 31:24
23:16
15:8
7:0
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Host drives DQ[7:0] and the memory drives RWDS.
CLK, NCLK
RWDS
DQ[7:0]
Memory drives DQ[7:0] and RWDS.
tw(CS)
tv(RWDS)
tv(CLK)
tv(DS)
tv(DQ)
th(CLK)
th(DS)
tv(OUT)
th(OUT)
th(DQ)
ts(DQ)
STM32H7B0xB
Operating conditions
DS13196 - Rev 7
page 126/205



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