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AT25SF321B データシート(PDF) 10 Page - Renesas Technology Corp |
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AT25SF321B データシート(HTML) 10 Page - Renesas Technology Corp |
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10 / 63 page ![]() DS-AT25SF321B-179 Rev. F Page 10 2022-06-03 © 2022 Renesas Electronics AT25SF321B Datasheet 4. Memory Array To provide the greatest flexibility, the memory array of the AT25SF321B can be erased in four levels of granularity, including a full-chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates each erase level. |
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