AT25SF321B datasheet(21/63 Pages) RENESAS

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DS-AT25SF321B-179 Rev. F

Page 21

2022-06-03

AT25SF321B Datasheet

7.5

Quad-I/O Fast Read Array (EBh)

The Quad-I/O Fast Read Array command is similar to the Quad-Output Fast Read Array command. It allows four

bits of address to be clocked into the device on every clock cycle, rather than just one.

To perform the Quad-I/O Read Array operation, the CS pin must first be asserted; then, the opcode EBh must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to

specify the location of the first byte to read within the memory array. Following the three address bytes, a single

mode byte must also be clocked into the device.

After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles

output data on the I/O3-0 pins. The data is output with the MSB of a byte first, and the MSB is output on the I/O3

pin. During the first clock cycle, bit 7 of the first data byte is output on the I/O3 pin while bits 6, 5, and 4 of the same

data byte are output on the I/O2, I/O1 and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of

the first data byte are output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues with each

byte of data being output after every two clock cycles.

When the last byte (3FFFFFh) of the memory array has been read, the device continues reading from the

beginning of the array (000000h). No delays are incurred when wrapping around from the end of the array to the

beginning of the array. Deasserting the CS pin terminates the read operation and puts the I/O3, I/O2, I/O1 and I/O0

pins into a high-impedance state. The CS pin can be deasserted at any time and does not require a full byte of

data to be read. The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read

Array command.

Figure 11. Quad-I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)

I/O0

(SI)

SCK

I/O1

(SO)

MSB

11101011

410 11

819

17 18

Opcode

A20 A16 A12 A8

A23-A16 A15-A8

A21 A17 A13 A9

21 22

Byte 1

Byte 2

I/O2

(WP)

A22 A18 A14 A10

D2 D6

I/O3

(HOLD)

A23 A19 A15 A11

D3 D7

14 15

A4 A0 M4 M0

A7-A0

M7-M0

A6 A2 M6 M2

A7 A3 M7 M3

A5 A1 M5 M1

Dummy

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