FS6407 datasheet(31/111 Pages) NXP

31 / 111 page

NXP Semiconductors

FS6407/FS6408

6.3

Deep fail-safe state

The Fail-safe state machine monitors the RSTB pin of the device and count the number of reset(s) happening in case of fault detection

(see Reset error counter). As soon as either the reset error counter reach its final value or the RESET pin remains asserted low for more

than 8.0 s, the device moves to Deep Fail-safe state, identified by the “Wait Deep Fail-safe” state in the functional state diagram

(Figure 10).

When the device is in Deep Fail-safe state, all the regulators are OFF. To exit this state, a Key OFF / Key ON action is needed. IO_0 is

usually connected to key signal. Key OFF (IO_0 low) moves the device to LPOFF-Deep FS, and Key ON (IO_0 high) wakes up the device.

The final value of the reset error counter can be configured to 2 or 6 in the register INIT FSSM 2. During power up phase, the 8.0 s timer

starts when the Fail-safe state machine enters in the “Select pin config detection” state and stop when the RSTB pin is released. During

“INIT FS” state, the 8.0 s timer can be disabled in the register INIT SUPERVISOR 2. During “Normal WD running” state, the 8.0 s timer is

activated at each RSTB pin assertion.

FS6407 データシート(PDF) 31 Page - NXP Semiconductors