5

Functional Pin Description

UGATE (Pin 1), (Pin 16 QFN)

Upper gate drive output. Connect to gate of high-side power

N-Channel MOSFET.

BOOT (Pin 2), (Pin 2 QFN)

Floating bootstrap supply pin for the upper gate drive.

Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to

turn on the upper MOSFET. A resistor in series with boot

capacitor is required in certain applications to reduce ringing

on the BOOT pin. See the Internal Bootstrap Device section

under DESCRIPTION for guidance in choosing the

appropriate capacitor and resistor values.

PWM (Pin 3), (Pin 3 QFN)

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation, see the

three-state PWM Input section under DESCRIPTION for further

details. Connect this pin to the PWM output of the controller.

GND (Pin 4), (Pin 4 QFN)

Bias and reference ground. All signals are referenced to this

node.

PGND (Pin 5 QFN Package Only)

This pin is the power ground return for the lower gate driver.

LGATE (Pin 5), (Pin 7 QFN)

Lower gate drive output. Connect to gate of the low-side

power N-Channel MOSFET.

VCC (Pin 6), (Pin 9 QFN)

Connect this pin to a +12V bias supply. Place a high quality

bypass capacitor from this pin to GND.

LVCC (Pin 10 QFN Package Only)

Lower gate driver supply voltage.

PVCC (Pin 7), (Pin 11 QFN)

For the HIP6601A and the HIP6604, this pin supplies the

upper gate drive bias. Connect this pin from +12V down to

+5V.

For the HIP6603A, this pin supplies both the upper and

lower gate drive bias. Connect this pin to either +12V or +5V.

PHASE (Pin 8), (Pin 14 QFN)

Connect this pin to the source of the upper MOSFET and the

drain of the lower MOSFET. The PHASE voltage is

monitored for adaptive shoot-through protection. This pin

also provides a return path for the upper gate drive.

Description

Operation

Designed for versatility and speed, the HIP6601A, HIP6603A

and HIP6604 dual MOSFET drivers control both high-side and

low-side N-Channel FETs from one externally provided PWM

signal.

The upper and lower gates are held low until the driver is

initialized. Once the VCC voltage surpasses the VCC Rising

Threshold (See Electrical Specifications), the PWM signal

takes control of gate transitions. A rising edge on PWM

initiates the turn-off of the lower MOSFET (see Timing

Diagram). After a short propagation delay [tPDLLGATE], the

lower gate begins to fall. Typical fall times [tFLGATE] are

provided in the Electrical Specifications section. Adaptive

shoot-through circuitry monitors the LGATE voltage and

determines the upper gate delay time [tPDHUGATE] based

on how quickly the LGATE voltage drops below 2.2V. This

prevents both the lower and upper MOSFETs from

conducting simultaneously or shoot-through. Once this delay

period is complete the upper gate drive begins to rise

[tRUGATE] and the upper MOSFET turns on.

Timing Diagram

PWM

UGATE

LGATE

tPDLLGATE

tFLGATE

tPDHUGATE

tRUGATE

tPDLUGATE

tFUGATE

tPDHLGATE

tRLGATE

HIP6601A, HIP6603A, HIP6604