7

be performed to ensure safe operation at the desired

frequency for the selected MOSFETs. The power dissipated

by the driver is approximated as:

where fsw is the switching frequency of the PWM signal. VU

and VL represent the upper and lower gate rail voltage. QU

and QL is the upper and lower gate charge determined by

MOSFET selection and any external capacitance added to

the gate pins. The IDDQ VCC product is the quiescent power

of the driver and is typically 30mW.

The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the

internal bootstrap device also dissipates power on-chip

during the refresh cycle. Expressing this power in terms of

the upper MOSFET total gate charge is explained below.

The bootstrap device conducts when the lower MOSFET or

its body diode conducts and pulls the PHASE node toward

GND. While the bootstrap device conducts, a current path is

formed that refreshes the bootstrap capacitor. Since the

upper gate is driving a MOSFET, the charge removed from

the bootstrap capacitor is equivalent to the total gate charge

of the MOSFET. Therefore, the refresh power required by

the bootstrap capacitor is equivalent to the power used to

charge the gate capacitance of the MOSFET.

where QLOSS is the total charge removed from the bootstrap

capacitor and provided to the upper gate load.

The 1.05 factor is a correction factor derived from the

following characterization. The base circuit for characterizing

the drivers for different loading profiles and frequencies is

provided. CU and CL are the upper and lower gate load

capacitors. Decoupling capacitors [0.15

µF] are added to the

PVCC and VCC pins. The bootstrap capacitor value is

0.01

µF.

In Figure 1, CU and CL values are the same and frequency

is varied from 50kHz to 2MHz. PVCC and VCC are tied

together to a +12V supply. Curves do exceed the 800mW

cutoff, but continuous operation above this point is not

recommended.

Figure 2 shows the dissipation in the driver with 3nF loading

on both gates and each individually. Note the higher upper

gate power dissipation which is due to the bootstrap device

refresh cycle. Again PVCC and VCC are tied together and to

a +12V supply.

Test Circuit

The impact of loading on power dissipation is shown in

Figure 3. Frequency is held constant while the gate

capacitors are varied from 1nF to 5nF. VCC and PVCC are

tied together and to a +12V supply. Figures 4 through 6

show the same characterization for the HIP6603A with a

+5V supply on PVCC and VCC tied to a +12V supply.

P1.05f

sw

3

2

---V

UQU

V

LQL

+





I

DDQ VCC

+

=

P

REFRESH

1

2

---f

SWQLOSS

V

PVCC

1

2

---f

SWQU

V

U

==

BOOT

UGATE

PHASE

LGATE

PWM

PVCC

GND

VCC

0.15

µF

0.15

µF

100k

Ω

2N7002

2N7002

0.01

µF

CL

CU

+5V OR +12V

+12V

+5V OR +12V

FIGURE 1. POWER DISSIPATION vs FREQUENCY

1000

800

600

400

200

0

500

1000

1500

2000

FREQUENCY (kHz)

CU = CL = 3nF

VCC = PVCC = 12V

CU = CL = 1nF

CU = CL = 2nF

CU = CL = 4nF

CU = CL = 5nF

FIGURE 2. 3nF LOADING PROFILE

1000

800

600

400

200

0

500

1000

1500

2000

FREQUENCY (kHz)

CU = CL = 3nF

VCC = PVCC = 12V

CU = 3nF

CU = 0nF

CL = 0nF

CL = 3nF

HIP6601A, HIP6603A, HIP6604