MPC602ECSLASHD datasheet(13/26 Pages) NXP

部品番号	MPC602EC/D

部品情報	PowerPC 602TM RISC Microprocessor Hardware Specification

PDF	26 Pages

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メーカー	NXP [NXP Semiconductors]

ホームページ	http://www.nxp.com

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PowerPC 602 RISC Microprocessor Hardware Specifications

Figure 5 provides the JTAG clock input timing diagram.

Figure 5. Clock Input Timing Diagram

Figure 6 provides the TRST timing diagram.

Figure 6. TRST Timing Diagram

TCK to output high impedance

TMS, TDI data setup time

—

TMS, TDI data hold time

—

TCK to TDO data valid

TCK to TDO high impedance

Notes:

1. TRST is an asynchronous signal. The setup time is for test purposes only.

2. Non-test signal input timing with respect to TCK.

3. Non-test signal output timing with respect to TCK.

Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)

Vdd = 3.3

± 10% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 °C

Num

Characteristic

Min

Max

Unit

Notes

TCK

VM = Midpoint Voltage (1.4 V)

TRST

TCK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC602EC/D データシート(PDF) 13 Page - NXP Semiconductors