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ICS9LPR502 データシート(PDF) 22 Page - Renesas Technology Corp |
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ICS9LPR502 データシート(HTML) 22 Page - Renesas Technology Corp |
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22 / 30 page  IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 Advance Information ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR 22 Datasheet Byte 10 CK505 Rev 0.85 functions (ICS Rev H silicon and higher) Bit Pin Name Description Type Default 7 SRC5_EN Readback Readback of SRC5 enable latch R Latch 6 Reserved RW 0 5 Reserved RW 0 4 Reserved RW 0 3 Reserved RW 0 2 Reserved RW 0 1 CPU 1 Stop Enable Enables control of CPU1 with CPU_STOP# RW 1 0 CPU 0 Stop Enable Enables control of CPU 0 with CPU_STOP# RW 1 Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher) Bit Pin Name Description Type Default 7 Reserved RW 0 6 Reserved RW 0 5 Reserved RW 0 4 Reserved RW 0 3 CPU2_iAMT_EN Enables CPU2(ITP) output in iAMT state (M1) RW 0 2 CPU1_iAMT_EN Enables CPU1 output in iAMT state (M1) RW 1 1 PCIe-Gen2 PCIe-Gen2 status R 0 0 CPU2 Stop Enable Enables control of CPU2(ITP) with CPU_STOP# RW 1 Byte 12 Byte Count Register Bit Pin Name Description Type Default 7 Reserved RW 0 6 Reserved RW 0 5 BC5 RW 0 4 BC4 RW 0 3 BC3 RW 1 2 BC2 RW 1 1 BC1 RW 0 0 BC0 RW 1 Byte 13 CK505 PLL1 M/N Programming Register Bit Pin Name Description Type Default 7 N Div8 N Divider 8 RW X 6 N Div9 N Divider 9 RW X 5 M Div5 RW X 4 M Div4 RW X 3 M Div3 RW X 2 M Div2 RW X 1 M Div1 RW X 0 M Div0 RW X Byte 14 CK505 PLL1 M/N Programming Register Bit Pin Name Description Type Default 7 N Div7 RW X 6 N Div6 RW X 5 N Div5 RW X 4 N Div4 RW X 3 N Div3 RW X 2 N Div2 RW X 1 N Div1 RW X 0 N Div0 RW X Reserved - - - - - - - - - - - - - - - - 01 - - - - - - - - - - - 01 - - Stoppable 01 Off in iAMT non-Gen2 Free Running TBD TBD TBD TBD Free running in iAMT Free running in iAMT PCIe Gen2 compliant TBD TBD TBD Off in iAMT Stoppable 01 TBD TBD Free Running Free Running SRC5 Enabled TBD TBD TBD TBD TBD Stoppable TBD TBD TBD TBD 01 CPU/PCI Stop Enabled The decimal representation of M and N Divider in Byte 13 and 14 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. - - - The decimal representation of M and N Divider in Byte 13 and 14 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. Read Back byte count register, max bytes = 32 Reserved |
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