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ICS9LPRS502 データシート(PDF) 16 Page - Renesas Technology Corp

部品番号 ICS9LPRS502
部品情報  56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR
PDF  30 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS9LPRS502 データシート(HTML) 16 Page - Renesas Technology Corp

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IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
16
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
11
1
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Reserved
100.00
33.33
14.318
48.00
96.00
Table 1: CPU Frequency Select Table
Pin 17
Pin 18
Spread
MHz
MHz
%
00
0
0
0
0
0
1
100.00
100.00
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0
0
1
0
100.00
100.00
0.5% Down Spread
Only SRCCLK1 from PLL3
0
0
1
1
100.00
100.00
1% Down Spread
Only SRCCLK1 from PLL3
0
1
0
0
100.00
100.00
1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0
1
100.00
100.00
2% Down Spread
Only SRCCLK1 from PLL3
0
1
1
0
100.00
100.00
2.5% Down Spread
Only SRCCLK1 from PLL3
01
1
1
N/A
N/A
N/A
N/A
1
0
0
0
24.576
24.576
None
24.576Mhz on SE1 and SE2
1
0
0
1
24.576
98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
1
0
1
0
98.304
98.304
None
98.304Mhz on SE1 and SE2
1
0
1
1
27.000
27.000
None
27Mhz on SE1 and SE2
1
1
0
0
25.000
25.000
None
25Mhz on SE1 and SE2
11
0
1
N/A
N/A
N/A
N/A
11
1
0
N/A
N/A
N/A
N/A
11
1
1
N/A
N/A
N/A
N/A
Comment
PLL 3 disabled
B1b1
B1b4
B1b3
B1b2
Table 2: PLL3 Quick Configuration



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