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ICS1893CFILF データシート(PDF) 118 Page - Renesas Technology Corp

部品番号 ICS1893CFILF
部品情報  3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
PDF  127 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1893CFILF データシート(HTML) 118 Page - Renesas Technology Corp

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ICS1893CF, Rev. K, 05/13/10
May, 2010
118
Chapter 9 DC and AC Operating Conditions
ICS1893CF Data Sheet - Release
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
9.5.16 Reset: Hardware Reset and Power-Down
Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 9-17 shows the timing diagram for the time periods.
Figure 9-17. Hardware Reset and Power-Down Timing Diagram
Table 9-23. Hardware Reset and Power-Down Timing
Time
Period
Parameter
Condi-
tions
Min.
Typ. Max. Units
t1
RESETn Active to Device Isolation and Initialization
–
–
60
–
ns
t2
Minimum RESETn Pulse Width
–
500
40
–
ns
t3
RESETn Released to TXCLK Valid
–
–
35
500
ms
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)



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